`include "common_header.verilog"

//  *************************************************************************
//  File : tx_block_type_10l.v
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized Reproduction or Use is Expressly Prohibited. 
//  Copyright (c) 2001 Morethanip
//  MorethanIP GmbH, GERMANY
//  info@morethanip.com
//  *************************************************************************
//  Version: $Id: tx_block_type_10l.v,v 1.1.1.1 2014/07/15 08:12:14 dk Exp $
//  Author : Serge S.
//  Initial: 01/02/2002
//  *************************************************************************
// 
//  Description: 10G Base-R PCS Transmit Encoder: block type definition 
// 
//  *************************************************************************

module tx_block_type_10l (

   reset,
   clk,
   clk_ena,
   tx_d_out,
   tx_c_out,
   data_out,
   class_block,
   t_type_c,
   t_type_s,
   t_type_t,
   t_type_d,
   t_type_e,
   `ifdef MTIPPCS_EEE_ENA
   t_type_li,   
   `endif
   loc_fault,
   rem_fault );

input   reset;                  //  asynch reset
input   clk;                    //  system clock     
input   clk_ena;                //  clock enable
input   [63:0] tx_d_out;        //  Data from XGMII bus
input   [7:0] tx_c_out;         //  Control lane from XGMII bus
output  [63:0] data_out;        //  Data out
output  [3:0] class_block;      //  Class block (Data block format Fig 49-7)
output  t_type_c;               //   C Block type received
output  t_type_s;               //   S Block type received
output  t_type_t;               //   T Block type received
output  t_type_d;               //   D Block type received
output  t_type_e;               //   E Block type received
`ifdef MTIPPCS_EEE_ENA
output  t_type_li;              //   LI Block type received   
`endif
output  loc_fault;              //  Local Fault
output  rem_fault;              //  Remote Fault

reg     [63:0] data_out; 
 
reg     [3:0] class_block; 
reg     t_type_c; 
reg     t_type_s; 
reg     t_type_t; 
reg     t_type_d; 
`ifdef MTIPPCS_EEE_ENA
wire    t_type_li;  
`endif
wire    t_type_e; 
reg     loc_fault;
reg     rem_fault;


// =============================================================
wire    [63:0] tx_d_out_s;      //  Data from XGMII bus
wire    [7:0] tx_c_out_s;       //  Control lane from XGMII bus

// 
// 
// ----------------------
//  C TYPE data
// ----------------------
wire    [7:0] ca_lane_nxt;      //  Not O, S, T and E character in lane 0 to 7 ?
wire    [7:0] ca_lane;          //  Not O, S, T and E character in lane 0 to 7 ?
reg     ordered_set_0_nxt;      //  Ordered_set character in lane 0
reg     ordered_set_4_nxt;      //  Ordered_set character in lane 4
wire    ordered_set_0;          //  Ordered_set character in lane 0
wire    ordered_set_4;          //  Ordered_set character in lane 4
wire    [7:0] not_o_s_t_nxt;    //  Not O, S and T character in lane 0 to 7 ?
wire    [7:0] not_o_s_t;        //  Not O, S and T character in lane 0 to 7 ?
reg     [3:0] t_type_c_s_nxt;   //   C Block type received
wire    [3:0] t_type_c_s;       //   C Block type received
reg     t_type_c_s_comb_nxt;    //  ORed t_type_c_s
wire    t_type_c_s_comb;        //  ORed t_type_c_s
// 
// ----------------------
//  S TYPE data
// ----------------------
wire    [7:0] data_caract_nxt;  //  Data caracter 0 to 7
wire    [7:0] data_caract;      //  Data caracter 0 to 7
reg     start_0_nxt;            //  Start Caracter in lane 0
reg     start_4_nxt;            //  Start Caracter in lane 4
wire    start_0;                //  Start Caracter in lane 0
wire    start_4;                //  Start Caracter in lane 4
reg     [2:0] t_type_s_s_nxt;   //   S Block type received
wire    [2:0] t_type_s_s;       //   S Block type received
reg     t_type_s_s_comb_nxt;    //  or of t_type_s_s
wire    t_type_s_s_comb;        //  or of t_type_s_s
// 
// ------------------------
//  T TYPE data
// ----------------------
reg     [7:0] t_caract_nxt;     //  Terminal caracter 0 to 7
wire    [7:0] t_caract;         //  Terminal caracter 0 to 7
wire    [7:0] t_type_t_s;       //   T Block type received
reg     [7:0] t_type_t_s_nxt;   //   T Block type received
wire    t_type_t_s_detect; 
reg     t_type_t_s_detect_nxt; 
// 
// ------------------------
//  T TYPE data
// ----------------------
reg     t_type_d_s_nxt;         //   D Block type received
wire    t_type_d_s;             //   D Block type received
wire    t_type_d_s_r;           //   D Block type received
// 
// ------------------------
//  Data Class
// ----------------------
wire    [15:0] class_code;      //  Define the class code
reg     [15:0] class_code_nxt;  //  Define the class code
// 

reg     t_type_d_s_r2;      
reg     t_type_s_s_comb_r;  
reg     t_type_t_s_detect_r;
reg     t_type_c_s_comb_r;  




// verify that code is one of the known control codes from Table 49-1 (including /E/)
// ----------------------------------------------------------------------------------
function CX_CHECK;
input [7:0] c;        
begin
        // allow all codes including reserved

        if (c == 8'h 07  |
`ifdef MTIPPCS_EEE_ENA
            c == 8'h 06  | // LPI
`endif
                `ifdef ENA_CLAUSE49_RESERVED
            c == 8'h 1c  | // 2d: 1c
            c == 8'h 3c  | // 33: 3c
            c == 8'h 7c  | // 4b: 7c
            c == 8'h bc  | // 55: bc
            c == 8'h dc  | // 66: dc
            c == 8'h f7  | // 78: f7
                `endif
            c == 8'h fe )  // 1e
        begin
                CX_CHECK = 1'b 1;
        end
        else
        begin
                CX_CHECK = 1'b 0;
        end
end
endfunction

// verify that code is a valid control code from Table 49-1 except /O/, /S/, /T/, /E/
// used for T_BLOCK_TYPE=C definition a) where /E/ is excempted.
function CX_CHECK_C;
input [7:0] c;        
begin
        // allow all codes including reserved

        if (
            `ifdef ENA_CLAUSE49_RESERVED
            c == 8'h 1c  | // 2d: 1c
            c == 8'h 3c  | // 33: 3c
            c == 8'h 7c  | // 4b: 7c
            c == 8'h bc  | // 55: bc
            c == 8'h dc  | // 66: dc
            c == 8'h f7  | // 78: f7
                `endif
            c == 8'h 07 )
        begin
                CX_CHECK_C = 1'b 1;
        end
        else
        begin
                CX_CHECK_C = 1'b 0;
        end
end
endfunction



always @*
   begin : p_data
      data_out = tx_d_out_s;		 
   end

assign tx_d_out_s = tx_d_out; //  Data from XGMII bus
assign tx_c_out_s = tx_c_out; //  Control lane from XGMII bus
 
 `ifdef MTIPPCS_EEE_ENA

wire    t_type_li_s; 
reg     t_type_li_s_r; 
wire [7:0] lpi_lane;
wire    lpi_lane3to0;
wire    lpi_lane7to4;

assign lpi_lane = {
        (tx_d_out_s[63:56] == 8'h 06 & tx_c_out_s[7] == 1'b 1),
        (tx_d_out_s[55:48] == 8'h 06 & tx_c_out_s[6] == 1'b 1),
        (tx_d_out_s[47:40] == 8'h 06 & tx_c_out_s[5] == 1'b 1),
        (tx_d_out_s[39:32] == 8'h 06 & tx_c_out_s[4] == 1'b 1),  
        (tx_d_out_s[31:24] == 8'h 06 & tx_c_out_s[3] == 1'b 1),
        (tx_d_out_s[23:16] == 8'h 06 & tx_c_out_s[2] == 1'b 1),
        (tx_d_out_s[15:8]  == 8'h 06 & tx_c_out_s[1] == 1'b 1),
        (tx_d_out_s[7:0]   == 8'h 06 & tx_c_out_s[0] == 1'b 1) };

assign lpi_lane3to0 = &lpi_lane[3:0];
assign lpi_lane7to4 = &lpi_lane[7:4];

assign t_type_li_s = &lpi_lane;

always @*
begin : p_li

      t_type_li_s_r = t_type_li_s;

end

assign t_type_li = t_type_li_s_r;

`endif	

// =====================================================================
//   class Block 
// =====================================================================
always @(t_type_d_s or t_type_c_s or t_type_t_s or t_type_s_s
        `ifdef MTIPPCS_EEE_ENA
        or t_type_li_s
        `endif
        )
   begin : p_class_code_nxt
        class_code_nxt = {     t_type_t_s[7], t_type_t_s[6], t_type_t_s[5], t_type_t_s[4], 
	                        t_type_t_s[3], t_type_t_s[2], t_type_t_s[1], t_type_t_s[0], 
	                        t_type_c_s[1], t_type_s_s[2], t_type_c_s[3], t_type_s_s[1], 
	                        t_type_s_s[0], t_type_c_s[2], 
                       `ifdef MTIPPCS_EEE_ENA
                               (t_type_c_s[0] | t_type_li_s), 
                       `else
                                t_type_c_s[0], 
                       `endif	
	                        t_type_d_s};	
   end

// -------------------------
//  Define the class code
// -------------------------
assign class_code = class_code_nxt;

always @*
begin
        case (class_code)
        16'h 0001: class_block = 4'h 0;
        16'h 0002: class_block = 4'h 1;
        16'h 0004: class_block = 4'h 2;
        16'h 0008: class_block = 4'h 3;
        16'h 0010: class_block = 4'h 4;
        16'h 0020: class_block = 4'h 5;
        16'h 0040: class_block = 4'h 6;
        16'h 0080: class_block = 4'h 7;
        16'h 0100: class_block = 4'h 8;
        16'h 0200: class_block = 4'h 9;
        16'h 0400: class_block = 4'h a;
        16'h 0800: class_block = 4'h b;
        16'h 1000: class_block = 4'h c;
        16'h 2000: class_block = 4'h d;
        16'h 4000: class_block = 4'h e;
        16'h 8000: class_block = 4'h f;
        default:   class_block = 4'h 1; // all control
        endcase        
end

	                                         
//  =====================================================================
//  E Block type received
//  =====================================================================

always @*
   begin
        t_type_d_s_r2           = t_type_d_s_r; 
        t_type_s_s_comb_r       = t_type_s_s_comb; 
	t_type_t_s_detect_r     = t_type_t_s_detect; 
	t_type_c_s_comb_r       = t_type_c_s_comb;
   end


assign  t_type_e = (t_type_d_s_r2 == 1'b 0 & t_type_s_s_comb_r == 1'b 0 &  
                    t_type_t_s_detect_r == 1'b 0 & t_type_c_s_comb_r == 1'b 0
                `ifdef MTIPPCS_EEE_ENA
                    & t_type_li_s_r == 1'b 0 
                `endif                    
                    )? 1'b1: 1'b0;

// =====================================================================
//  D Block type received
// =====================================================================
always @(data_caract)
   begin : p_d_block_nxt
   if (data_caract[7:0] == 8'b 00000000)
      begin
      t_type_d_s_nxt = 1'b 1;	
      end
   else
      begin
      t_type_d_s_nxt = 1'b 0;	
      end
   end

assign t_type_d_s = t_type_d_s_nxt; 
assign t_type_d_s_r = t_type_d_s;
 
always @*
   begin : p_d_block
      t_type_d = t_type_d_s_r;	
   end

// =====================================================================
//  Check that Termination received and no other 
// =====================================================================
//  T Block type received
// =====================================================================

always @(tx_d_out_s or tx_c_out_s)
   begin : p_t_caract_nxt
   if (tx_d_out_s[7:0] == 8'b 11111101 & tx_c_out_s[0] == 1'b 1)
      begin
      t_caract_nxt[0] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[0] = 1'b 0;	
      end
   if (tx_d_out_s[15:8] == 8'b 11111101 & tx_c_out_s[1] == 1'b 1)
      begin
      t_caract_nxt[1] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[1] = 1'b 0;	
      end
   if (tx_d_out_s[23:16] == 8'b 11111101 & tx_c_out_s[2] == 1'b 1)
      begin
      t_caract_nxt[2] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[2] = 1'b 0;	
      end
   if (tx_d_out_s[31:24] == 8'b 11111101 & tx_c_out_s[3] == 1'b 1)
      begin
      t_caract_nxt[3] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[3] = 1'b 0;	
      end
   if (tx_d_out_s[39:32] == 8'b 11111101 & tx_c_out_s[4] == 1'b 1)
      begin
      t_caract_nxt[4] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[4] = 1'b 0;	
      end
   if (tx_d_out_s[47:40] == 8'b 11111101 & tx_c_out_s[5] == 1'b 1)
      begin
      t_caract_nxt[5] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[5] = 1'b 0;	
      end
   if (tx_d_out_s[55:48] == 8'b 11111101 & tx_c_out_s[6] == 1'b 1)
      begin
      t_caract_nxt[6] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[6] = 1'b 0;	
      end
   if (tx_d_out_s[63:56] == 8'b 11111101 & tx_c_out_s[7] == 1'b 1)
      begin
      t_caract_nxt[7] = 1'b 1;	
      end
   else
      begin
      t_caract_nxt[7] = 1'b 0;	
      end
   end

// ------------------------------
//  Terminal in lane 0 to 7 ? 
// ------------------------------
assign t_caract = t_caract_nxt; //  Terminal caracter 0 to 7

always @(not_o_s_t or data_caract or t_caract)
   begin : p_t_type_t_s_nxt
   if (t_caract[0] == 1'b 1 & not_o_s_t[7:1] == 7'b 1111111)
      begin
//  class 8  
      t_type_t_s_nxt[0] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[0] = 1'b 0;	
      end
// 
   if (t_caract[1] == 1'b 1 & not_o_s_t[7:2] == 6'b 111111 & 
	data_caract[0] == 1'b 0)
      begin
//  class 9  
      t_type_t_s_nxt[1] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[1] = 1'b 0;	
      end
// 
   if (t_caract[2] == 1'b 1 & not_o_s_t[7:3] == 5'b 11111 & 
	data_caract[1:0] == 2'b 00)
      begin
//  class 10  
      t_type_t_s_nxt[2] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[2] = 1'b 0;	
      end
// 
   if (t_caract[3] == 1'b 1 & not_o_s_t[7:4] == 4'b 1111 & 
	data_caract[2:0] == 3'b 000)
      begin
//  class 11
      t_type_t_s_nxt[3] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[3] = 1'b 0;	
      end
// 
   if (t_caract[4] == 1'b 1 & not_o_s_t[7:5] == 3'b 111 & 
	data_caract[3:0] == 4'b 0000)
      begin
//  class 12
      t_type_t_s_nxt[4] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[4] = 1'b 0;	
      end
// 
   if (t_caract[5] == 1'b 1 & not_o_s_t[7:6] == 2'b 11 & 
	data_caract[4:0] == 5'b 00000)
      begin
//  class 13
      t_type_t_s_nxt[5] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[5] = 1'b 0;	
      end
// 
   if (t_caract[6] == 1'b 1 & not_o_s_t[7] == 1'b 1 & 
	data_caract[5:0] == 6'b 000000)
      begin
//  class 14
      t_type_t_s_nxt[6] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[6] = 1'b 0;	
      end
// 
   if (t_caract[7] == 1'b 1 & data_caract[6:0] == 7'b 0000000)
      begin
//  class 15
      t_type_t_s_nxt[7] = 1'b 1;	
      end
   else
      begin
      t_type_t_s_nxt[7] = 1'b 0;	
      end
   end


// -------------------------
//   T Block type received
// -------------------------   
assign t_type_t_s = t_type_t_s_nxt; //  Terminal caracter 0 to 7
always @(t_type_t_s)
   begin : p_t_block_common_nxt
   if (t_type_t_s[7] == 1'b 1 | t_type_t_s[6] == 1'b 1 | 
	t_type_t_s[5] == 1'b 1 | t_type_t_s[4] == 1'b 1 | 
	t_type_t_s[3] == 1'b 1 | t_type_t_s[2] == 1'b 1 | 
	t_type_t_s[1] == 1'b 1 | t_type_t_s[0] == 1'b 1)
      begin
      t_type_t_s_detect_nxt = 1'b 1;	
      end
   else
      begin
      t_type_t_s_detect_nxt = 1'b 0;	
      end
   end

assign t_type_t_s_detect = t_type_t_s_detect_nxt; //  Terminal caracter 0 to 7

always @*
   begin : p_t_type_t
      t_type_t = t_type_t_s_detect;	
   end

assign data_caract_nxt = tx_c_out_s;
 
assign data_caract = data_caract_nxt; //  Terminal caracter 0 to 7

// ------------------------------
//  Start Caracter in lane 0   
// ------------------------------

always @(tx_c_out_s or tx_d_out_s)
   begin : p_start_nxt_0
   if (tx_d_out_s[7:0] == 8'b 11111011 & tx_c_out_s[0] == 1'b 1)
      begin
      start_0_nxt = 1'b 1;	
      end
   else
      begin
      start_0_nxt = 1'b 0;	
      end
   end

// ------------------------------
//  Start Caracter in lane 4 
// ------------------------------

always @(tx_c_out_s or tx_d_out_s)
   begin : p_start_nxt_4
   if (tx_d_out_s[39:32] == 8'b 11111011 & tx_c_out_s[4] == 1'b 1)
      begin
      start_4_nxt = 1'b 1;	
      end
   else
      begin
      start_4_nxt = 1'b 0;	
      end
   end


assign start_0 = start_0_nxt; //  Start Caracter in lane 0
assign start_4 = start_4_nxt; //  Start Caracter in lane 4

always @(start_0 or start_4 or data_caract or not_o_s_t or ordered_set_0)
   begin : p_t_type_s_s_nxt
   if (start_4 == 1'b 1 & data_caract[7:5] == 3'b 000 & not_o_s_t[3:0] == 4'b 1111)
      begin
//  class 3
      t_type_s_s_nxt[0] = 1'b 1;	
      end
   else
      begin
      t_type_s_s_nxt[0] = 1'b 0;	
      end
// 
   if (start_4 == 1'b 1 & data_caract[7:5] == 3'b 000 & ordered_set_0 == 1'b 1)
      begin
//  class 4
      t_type_s_s_nxt[1] = 1'b 1;	
      end
   else
      begin
      t_type_s_s_nxt[1] = 1'b 0;	
      end
// 
   if (start_0 == 1'b 1 & data_caract[7:1] == 7'b 0000000)
      begin
//  class 6
      t_type_s_s_nxt[2] = 1'b 1;	
      end
   else
      begin
      t_type_s_s_nxt[2] = 1'b 0;	
      end
   end

// -------------------------
//   S Block type received
// -------------------------   
assign t_type_s_s = t_type_s_s_nxt;
 
always @(t_type_s_s)
   begin : p_t_type_s_s_comb_nxt
   if (t_type_s_s[0] == 1'b 1 | t_type_s_s[1] == 1'b 1 | 
	t_type_s_s[2] == 1'b 1)
      begin
      t_type_s_s_comb_nxt = 1'b 1;	
      end
   else
      begin
      t_type_s_s_comb_nxt = 1'b 0;	
      end
   end

// -------------------------
//   S Block type received
// -------------------------   
assign t_type_s_s_comb = t_type_s_s_comb_nxt;
 
always @*
   begin : p_s_block
      t_type_s = t_type_s_s_comb;	
   end

// ========================================================
//  C Block type received=============
// =====================================================================    
assign ca_lane_nxt[0] = CX_CHECK_C(tx_d_out_s[7:0])   == 1'b 1 & tx_c_out_s[0] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[1] = CX_CHECK_C(tx_d_out_s[15:8])  == 1'b 1 & tx_c_out_s[1] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[2] = CX_CHECK_C(tx_d_out_s[23:16]) == 1'b 1 & tx_c_out_s[2] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[3] = CX_CHECK_C(tx_d_out_s[31:24]) == 1'b 1 & tx_c_out_s[3] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[4] = CX_CHECK_C(tx_d_out_s[39:32]) == 1'b 1 & tx_c_out_s[4] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[5] = CX_CHECK_C(tx_d_out_s[47:40]) == 1'b 1 & tx_c_out_s[5] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[6] = CX_CHECK_C(tx_d_out_s[55:48]) == 1'b 1 & tx_c_out_s[6] == 1'b 1 ? 1'b 1 : 1'b 0;
assign ca_lane_nxt[7] = CX_CHECK_C(tx_d_out_s[63:56]) == 1'b 1 & tx_c_out_s[7] == 1'b 1 ? 1'b 1 : 1'b 0;
 
`ifdef MTIPPCS_EEE_ENA
assign ca_lane[3:0] = (lpi_lane3to0==1'b 1 & lpi_lane7to4==1'b 0) ? 4'b 1111 : ca_lane_nxt[3:0];
assign ca_lane[7:4] = (lpi_lane3to0==1'b 0 & lpi_lane7to4==1'b 1) ? 4'b 1111 : ca_lane_nxt[7:4];
`else
assign ca_lane = ca_lane_nxt;
`endif

always @(tx_d_out_s or tx_c_out_s)
   begin : p_ordered_set_nxt_0
   if ((tx_d_out_s[7:0] == 8'b 10011100 | tx_d_out_s[7:0] == 8'b 01011100) & 
	tx_c_out_s[3:0] == 4'b 0001)
      begin
      ordered_set_0_nxt = 1'b 1;	
      end
   else
      begin
      ordered_set_0_nxt = 1'b 0;	
      end
   end

// ---------------------------------
//  Ordered_set character in lane 0 (0x9c/0x5c) 
// ---------------------------------
always @(tx_d_out_s or tx_c_out_s)
   begin : p_ordered_set_nxt_4
   if ((tx_d_out_s[39:32] == 8'b 10011100 | tx_d_out_s[39:32] == 8'b 01011100) & 
	tx_c_out_s[7:4] == 4'b 0001)
      begin
      ordered_set_4_nxt = 1'b 1;	
      end
   else
      begin
      ordered_set_4_nxt = 1'b 0;	
      end
   end

// ---------------------------------
//  Ordered_set character in lane 0 (0x9c/0x5c) 
// ---------------------------------
assign ordered_set_0 = ordered_set_0_nxt; //  Ordered_set character in lane 0
assign ordered_set_4 = ordered_set_4_nxt; //  Ordered_set character in lane 4

assign not_o_s_t_nxt[0] = CX_CHECK(tx_d_out_s[7:0])   == 1'b 1 & tx_c_out_s[0] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[1] = CX_CHECK(tx_d_out_s[15:8])  == 1'b 1 & tx_c_out_s[1] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[2] = CX_CHECK(tx_d_out_s[23:16]) == 1'b 1 & tx_c_out_s[2] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[3] = CX_CHECK(tx_d_out_s[31:24]) == 1'b 1 & tx_c_out_s[3] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[4] = CX_CHECK(tx_d_out_s[39:32]) == 1'b 1 & tx_c_out_s[4] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[5] = CX_CHECK(tx_d_out_s[47:40]) == 1'b 1 & tx_c_out_s[5] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[6] = CX_CHECK(tx_d_out_s[55:48]) == 1'b 1 & tx_c_out_s[6] == 1'b 1 ? 1'b 1 : 1'b 0;
assign not_o_s_t_nxt[7] = CX_CHECK(tx_d_out_s[63:56]) == 1'b 1 & tx_c_out_s[7] == 1'b 1 ? 1'b 1 : 1'b 0;

assign not_o_s_t = not_o_s_t_nxt; //  Not O, S and T character in lane 0 to 7 ?

always @(ca_lane or ordered_set_0 or ordered_set_4 or not_o_s_t)
   begin : p_t_type_c_s_nxt
   if (ca_lane[7:0] == 8'b 11111111)
      begin
//  class 1
      t_type_c_s_nxt[0] = 1'b 1;	
      end
   else
      begin
      t_type_c_s_nxt[0] = 1'b 0;	
      end
// 
   if (ordered_set_0 == 1'b 1 & not_o_s_t[7:4] == 4'b 1111)
      begin
//  class 7
      t_type_c_s_nxt[1] = 1'b 1;	
      end
   else
      begin
      t_type_c_s_nxt[1] = 1'b 0;	
      end
// 
   if (ordered_set_4 == 1'b 1 & not_o_s_t[3:0] == 4'b 1111)
      begin
//  class 2
      t_type_c_s_nxt[2] = 1'b 1;	
      end
   else
      begin
      t_type_c_s_nxt[2] = 1'b 0;	
      end
// 
   if (ordered_set_0 == 1'b 1 & ordered_set_4 == 1'b 1)
      begin
//  class 5
      t_type_c_s_nxt[3] = 1'b 1;	
      end
   else
      begin
      t_type_c_s_nxt[3] = 1'b 0;	
      end
   end
// 
// 
// -------------------------
//   C Block type received
// -------------------------   
assign t_type_c_s = t_type_c_s_nxt; //   C Block type received

always @(t_type_c_s)
   begin : p_t_type_c_s_comb_nxt
   if (t_type_c_s[0] == 1'b 1 | t_type_c_s[1] == 1'b 1 | 
       t_type_c_s[2] == 1'b 1 | t_type_c_s[3] == 1'b 1)
      begin
      t_type_c_s_comb_nxt = 1'b 1;	
      end
   else
      begin
      t_type_c_s_comb_nxt = 1'b 0;	
      end
   end

// -------------------------
//   C Block type received
// -------------------------   
assign t_type_c_s_comb = t_type_c_s_comb_nxt; //   C Block type received

always @*
   begin : p_c_block
      t_type_c = t_type_c_s_comb;	
   end


//  Sequence Decoding
//  -----------------

always@(posedge reset or posedge clk)
   begin
   if (reset==1'b 1)
      begin
      loc_fault <= 1'b 0;
      rem_fault <= 1'b 0;
      end
   else if (clk_ena==1'b1)
      begin
      if ((tx_c_out_s[3:0]==4'b 0001 & tx_d_out_s[31:0] ==32'h 0100009C) |
          (tx_c_out_s[7:4]==4'b 0001 & tx_d_out_s[63:32]==32'h 0100009C))
         begin
         loc_fault <= 1'b 1;
         end
      else
         begin
         loc_fault <= 1'b 0;
         end

      if ((tx_c_out_s[3:0]==4'b 0001 & tx_d_out_s[31:0] ==32'h 0200009C) |
          (tx_c_out_s[7:4]==4'b 0001 & tx_d_out_s[63:32]==32'h 0200009C))
         begin
         rem_fault <= 1'b 1;
         end
      else
         begin
         rem_fault <= 1'b 0;
         end

      end
   end

endmodule // module tx_block_type_10l